High Speed PCB
Introduction
The term “high speed” is defined under different contexts and under applicable design practices, such as:
High speed digital: Rapid edge rates as encountered in signal rise time or fall time, whichever is less defines the signal as “high speed.” A rise or fall time of 1 ns implies a total signal bandwidth of 1 GHz or more, even with much lower switching speeds.
Signals superimposed on high-frequency carriers at multiple GHz are defined as “high speed RF.”
Systems with carrier frequencies at tens of GHz are defined as millimeter-wave designs.
The focus here is on PCB solutions for high-speed digital applications. Here technology evolution is driven by requirements to be
Smaller: Increased miniaturization in the core compute processing units leads to finer features and increased functionality and/or capacity on a given PCB leads to higher layer counts, as well as finer features.
Faster: Interconnect speed will often be the limiting factor, particularly at the package level. Per-lane signaling speeds need to continually increase and that implies extra signal bandwidths. Issues like losses and signal integrity will be critical.
Hotter and greener: Even with improvements in energy efficiency, heavier workloads from computing paradigms like machine learning and the need for increased overall capacity will drive up power consumption. Aside from supporting the necessary higher power delivery, PCBs will also have to accommodate new approaches to thermal management, such as immersion cooling.
Cheaper: For infrastructure electronics, costings consider more than the bill of materials (BOM) cost, but focus on the full lifecycle. Improved reliability is a major objective to drive down lifetime cost.
Key features of concern are as follows:
Trace interconnects: control of physical length is critical as it induces reflections and affects signal performance.
Fan outs, such as wire bonding, bumps and vias.
Interconnect substrates, return planes, interconnect media contribute towards signal performance.
PCB resistive and dissipation losses have an impact on the overall power budget.
The following dimensions contribute to success of high-speed interconnects:
Proper material selection
Surface finish technology
Layout simulation
PCB fabrication
Subsequent board assembly
Remaining back drill stub or stub-less designs.
Technical Needs, Gaps and Solutions
The technology issues surrounding High Speed PCBs, the associated needs, technology status of those needs, as well as gaps and challenges to overcome, are summarized below. The time period considered is from 2023 to 2033.
Some definitions:
Term | Definition |
|---|---|
GAP | This is what is missing or what below in performance, in today’s technology, to meet the need for year X. |
CHALLENGE | Why is it difficult to meet the need in year X? Typically, this is some particular technical consequence of that need that is inherently difficult. |
CURRENT TECHNOLOGY STATUS in year X | How well does today’s technology and solutions meet the need in year X? |
Technology Status Legend
For each need, the status of today’s technology is indicated by label and color as follows:
In-table color + label key | Description of Technology Status |
|---|---|
Solutions not known | Solutions not known at this time |
Solutions need optimization | Current solutions need optimization |
Solutions deployed or known | Solutions deployed or known today |
Not determined | TBD |
Table 1. High Speed PCBs Gaps, and Today’s Technology Status with Respect to Current and Future Needs
| ROADMAP TIMEFRAME | |||
TECHNOLOGY ISSUE | TODAY (2023) | 3 YEARS (2026) | 5 YEARS (2028) | 10 YEARS (2032) |
ISSUE: FREQUENCY DRIVERS | ||||
NEED | 400 Gb/ethernet (switch) | 800 Gbps/internet | 1.2-1.6 Tbps/internet | Unknown |
112 Gbps/data center | 224 Gbps/data center | 224 Gbps/data center | 448 Gbps/data center | |
CURRENT TECHNOLOGY STATUS | Stabilized | R&D and stabilized | Stabilized | Unknown |
GAP | Complexity and material availability and processibility | Unknown | ||
GAP | Simulation tools need further development | Unknown | ||
GAP | ||||
CHALLENGE | Signal rise time/integrity | Unknown | ||
CHALLENGE | Board mount | Front panel mount | Unknown | |
ISSUE: LINE CARD | ||||
NEED: Architectures High-layer count | High-layer count (26-32 layer) | High-layer count (36-52 layer) | High-layer count with complex high-density interconnect (HDI) (8+x+8) | Unknown |
CURRENT TECHNOLOGY STATUS | Deployed | Deployed | Equipment mix complexity needs solutions | Unknown |
GAP | Complexity and material availability and processibility | Complexity and existing and new material availability and processibility | Unknown | |
CHALLENGE | Reliability | Manufacturing Capacity by region | Unknown | |
CHALLENGE | Micro-via hole integrity, thermal reliability | Unknown | ||
CHALLENGE |
| Lead time for new facility builds | Unknown | |
CHALLENGE |
| Supply chain | Unknown | |
NEED: Dielectric | Ultra-low-loss | Extreme low loss | Thermo-plastic material | Unknown |
CURRENT TECHNOLOGY STATUS | Deployed | Limited deployment | In research and development | Unknown |
GAP | Availability of material and experience of use. The use of hybrid construction and compatibility must be addressed. | Availability | Unknown | |
CHALLENGE | Definition of ultra-low-loss | Manufacturing capacity | Unknown | |
CHALLENGE |
| Material availability (copper, glass) | Material availability | Unknown |
CHALLENGE |
| Material properties reliability | Unknown | |
CHALLENGE |
| Market pressure on design (miniaturization) | Unknown | |
NEED: Copper | Hyper very low profile (HVLP)2 and HVLP3/low etch oxide | HVLP3-HVLP5/no etch oxide plus resin-coated copper | Alternatives (resin-coated copper, semi-additives, other metals, etc.) | Unknown |
CURRENT TECHNOLOGY STATUS | Deployed | Limited, to be optimized | Solutions to be optimized | Unknown |
GAP | Definition of HVLP | How to define what is “smooth” vs “rough” | TBD | Unknown |
GAP | Methodology/metrology to characterize roughness is being developed | Metrology accuracy | Unknown | |
CHALLENGE | Standards needs | Unknown | ||
CHALLENGE | Adhesion (mechanical bonding) and methods to test |
| ||
CHALLENGE | Surface roughness, other physical properties | Unknown | ||
CHALLENGE | Cost of copper foil | Quantify benefits post no etch oxide. |
|
|
CHALLENGE | Signal integrity | Unknown | ||
CHALLENGE | Reliability and quality (delamination, mechanical robustness, etc.) | Unknown | ||
NEED: Glass | Low Dk | Lower Dk glass | No glass? New materials’ alternatives and architectures | New developments and materials (non-wovens [glass, non-glass], other reinforcements), hybrid structures |
CURRENT TECHNOLOGY STATUS | Deployed | Very limited, supply to be determined | Solutions to be optimized | No solutions |
GAP | None | Process maturity, processes at high temperatures, quality & stability | Reliability, time to qualify, ease of manufacturing for more flexible | |
GAP | None | Process maturity, processes at high temperatures, quality & stability | UL approval for films, non-woven alternates, other organics | |
CHALLENGE |
| Availability | Processability | |
CHALLENGE |
| Cost of investment for switch-over | ||
ISSUE: BACKPLANE/MIDPLANE | ||||
NEED: Architectures, inc. layer count, press fit, thickness | Up to 60 layers; impedance tolerance at 8% | Traces become wider, connectors become more complex, and press fit more difficult, tighter tolerances whole size and impedance (5%) | Backplane function moves from passive to active areas | |
CURRENT TECHNOLOGY STATUS | Solutions Deployed | Solutions need optimization | ||
GAP | Limited availability and capability (linewidth control over longer lengths and within panel and dielectric thickness control) | Design availability and coordination with mechanical, etc. multidisciplinary effort | Board design more complicated | |
CHALLENGE | Thickness, aspect ratio, registration, flatness control (no true horizontal, vertical features) | Complexity increases | Power distribution critical challenge (higher copper weights not always possible and liquid immersion cooling is needed) | |
CHALLENGE | Backplane/midplane definitions differ from proprietary to industry standards | Rack servers' physical realization | Hardware technologies combinations unclear | |
NEED: Dielectric | Ultra-low-loss | Extreme low loss | Thermo-plastic material | Unknown |
CURRENT TECHNOLOGY STATUS | Available materials increasing and use of hybrid stack-ups to avoid high cost | New materials | New materials | Innovation in out years |
GAP | Availability of materials and experience of use specially in hybrid applications. | Availability | ||
CHALLENGE | Cost to incremental improvements | Processability (mechanical processes, hybrid board de-smear, multiple materials complexity, etc.) | Processability | Cost to incremental improvements |
NEED: Copper | HVLP2 and HVLP3/low etch oxide | HVLP3 and HVLP4/no etch oxide | HVLP3 and HVLP4/no etch oxide and with chemical adhesion development | Unknown |
CURRENT TECHNOLOGY STATUS | Deployed | Maturing and more available | Maturing and more available | Unknown |
GAP |
|
|
|
|
CHALLENGE | Adhesion |
| ||
NEED: Glass | Low Dk | Lower Dk glass types with expanded offerings of glass style | New materials (non-woven or alternative reinforcement) | Unknown |
CURRENT TECHNOLOGY STATUS | Deployed | To be optimized for types and levels | Research ongoing | Unknown |
GAP |
|
|
|
|
CHALLENGE | Capacity development and supply chain | TBD based on market | ||
NEED: Glass Type for Skew Mitigation | 1027 spread glass | 1017 spread glass | Non-woven reinforcement technologies and hybrids (organic and inorganic woven together) | |
CURRENT TECHNOLOGY STATUS | Deployed | Limited deployment, to be optimized for volume | In research | To be developed |
GAP |
|
|
|
|
CHALLENGE | Availability with constrained supply Yield with thinner glass | New equipment and web handling, slower investment. Availability w constrained supply yield with thinner glass | ||
NEED: Reliability | Super-high Tg/low CTE | Super-high Tg/lower CTE | Super-high Tg | To be developed |
CURRENT TECHNOLOGY STATUS | Substrate-type materials properties are needed for PCB materials and supply is developing | |||
GAP | Affordability and availability in volume | |||
CHALLENGE | Market adoption by PCB laminate suppliers into main stream PCB supply chain | |||
NEED: Thickness | Aspect ratio = 20:1 | AR=40:1 | Not yet known | |
CURRENT TECHNOLOGY STATUS | Deployed | Low volume, to be optimized | Increase in sequential buildup boards | |
GAP | Not enough suppliers | Due to limits in plating and drilling technologies, new innovation needed | ||
CHALLENGE | Amount pulse plating process deployment investment and switch out, not deployed fully | Specialized plating needs, includes pulse plate but designs are different (more cellular, like IC vertical lines), investment in equipment, better drilling machines needed | New drill designs, and drill machines | Not yet known |
ISSUE: ENERGY (PERFORMANCE) | ||||
NEED | 300 W per | 600 W per chip package | 900 W per chip package | |
CURRENT TECHNOLOGY STATUS | Solutions exist | Solutions exist but need optimization | New materials needed | |
GAP | none | Materials with improved thermal conductivity, CTE and maximum operating temperatures | Better performing new solutions for thermal interface materials | |
CHALLENGE | Continued downward pressure on energy losses | |||
CHALLENGE | Thermal management | |||
CHALLENGE | Compatibility with liquids used in liquid cooling, e.g., immersion | |||
ISSUE: DEVICE PIN PITCH | Thicker line cards are 0.8 mm – 1.0 mm Thinner line cards are 0.6 mm Smaller handheld cards are 0.35 mm | Thicker line cards are 0.65 mm - 0.8mm Thinner line cards are 0.5 mm Smaller handheld cards are 0.3 mm | Thicker line cards are 0.5 mm - 0.65 mm Thinner line cards are <0.5 mm Smaller handheld cards are <0.3 mm | |
NEED: Registration | Thick D+9 mil Handheld D+4 mil (HDI) | Thick D+8 mil Handheld D+4 mil (HDI) | Thick D+7 mil (mix HDI) Handheld D+4 mil (HDI) | Thick D+6 mil (mix HDI) Handheld D+3 mil (HDI) |
CURRENT TECHNOLOGY STATUS | Solutions deployed | Solutions need optimization | Solutions not known | |
GAP | Lack of sophistication of equipment and materials (AI and ML solutions), long test lead times without an industry standard on tests. | Leadtime for developing solutions | ||
CHALLENGE | Achieving tighter tolerances allowance/variance percentages (materials, equipment, statistical process tolerance) with 100% check | EDA tools’ constraints due to adoption of front end (silicon) (mils to microns) and heterogeneous integration | ||
NEED: Aspect Ratio | HDI – 1:1 Thru holes 22:1 µVia 2:1 | HDI – 1.2:1 Thru holes 26:1 | ||
CURRENT TECHNOLOGY STATUS | Solutions need optimization | Solutions not known | ||
GAP | Lack of wide spread modern plating equipment | Adoption of modern plating equipment for wider use | Innovations in plating needed | |
CHALLENGE | Cost for installation and ramp | |||
ISSUE: DESIGN TOOLS FOR ROUTING | ||||
NEED | More sophisticated routing tools for miniaturization of designs. (Solutions coming from the chip-design world.) | Complete software suites required | AI-driven designs | |
CURRENT TECHNOLOGY STATUS | Assisted routing (batch routing) is the state of art versus auto-routing | Optimization of models |
| |
GAP | Limitations in current (software) SW solutions. Impedance characterization and control. | Design automation can run at odds with each company’s differentiation and proprietary (IP) | Hesitancy to adopt | |
CHALLENGE | Tradeoff decisions based on cost (prohibitive) of EDA tools versus better performance | |||
CHALLENGE | Constraints in definitions and executions and available knowledge base | |||
ISSUE: POWER DISTRIBUTION | ||||
NEED | Increased power to the chipsets, to be supported by the PCBs: Higher layer count (power and return planes), including asymmetrical stack-ups | Design driven by minimization of energy losses | ||
CURRENT TECHNOLOGY STATUS | OEMs drive supplier development to maintain market position (“preferred suppliers") (leading edge versus fast learner) | Standardization and convergence of material development allowing for more complexity | ||
GAP | Risk of less innovation | |||
GAP | “Reduce to practice” barriers: Sole source and material development and deployment | |||
CHALLENGE | Maintaining reliability, flatness (warpage) and coplanarity with all surface finishes, higher aspect ratios | |||
NEED | Better-conductivity (electrical) materials throughout the PCB stack | Better-conductivity (electrical) materials throughout the PCB stack: More available options that are more manufacturable | ||
CURRENT TECHNOLOGY STATUS | Solutions need optimization | |||
GAP | “Reduce to practice” barriers: Sole source and material development and deployment | |||
CHALLENGE | Performance improvement confirmation is design-dependent (not readily available) | Broadened landscape of competitive solutions | ||
NEED | Improved/new thermal conductivity materials throughout the PCB stack. | |||
CURRENT TECHNOLOGY STATUS | Solutions need optimization | |||
GAP | Optimization of existing resin-coated copper for buildup boards. In current environment it is not urgent yet but high power is needed for AI chipsets may drive the market and more development. | |||
CHALLENGE | Better thermal management | |||
Approaches to address Needs, Gaps and Challenges
Table 2 considers approaches to address the above needs and challenges. The evolution of these is projected out over a 10-year timeframe using technology readiness levels (TRLs).
In-table color key | Range of Technology Readiness Levels | Description |
|---|---|---|
2 | TRL: 1 to 4 | Levels involving research |
6 | TRL: 5 to 7 | Levels involving development |
9 | TRL: 8 to 9 | Levels involving deployment |
Table 2. High Speed PCB Potential Solutions
|
| EXPECTED TRL LEVEL | |||
TECHNOLOGY ISSUE | POTENTIAL SOLUTIONS | TODAY (2023) | 3 YEARS (2026) | 5 YEARS (2028) | 10 YEARS (2033) |
Frequency drivers | Material libraries (including new high-frequency materials such as Teflon) from PCB fabricators, simulation tools and processes for high frequencies at 800Gb/s | 7 | 8 | 9 | 9 |
| … 1.2-1.6Tb/s | 4 | 6 | 8 | 9 |
| … 1.6Tb/s and above | 3 | 4 | 5 | 8 |
Layer count | Drill size of 8 mils to attain multilayers technologies to be attained by necessary investment for capacity | 6 | 7 | 8 | 9 |
| New and extended regional manufacturing facilities | 4 | 5 | 6 | 8 |
Dielectrics | Development of new materials for high frequencies, e.g., new resin technologies such as Teflon | 8 | 9 | 9 | 9 |
| Development of new materials for high frequencies, e.g., new resin technologies such as liquid crystal polymers (LCPs) | 7 | 8 | 9 | 9 |
| Development of new materials for high frequencies, e.g., other new resin technologies such as thermo-plastic materials, etc. | 3 | 3 | 4 | 7 |
Dielectrics and Reinforcement | Injection of air via aerogels into the dielectrics, to lower the dielectric constant | 7 | 7 | 8 | 9 |
| Injection of air via glass beads into the dielectrics, to lower the dielectric constant | 4 | 5 | 6 | 8 |
Copper | Development of new materials for high frequencies (e.g., graphene) | 3 | 3 | 4 | 7 |
| Waveguide-based conductors | 4 | 5 | 6 | 7 |
| New chemical adhesion promoters for smoother finishes with low skin depths | 6 | 7 | 8 | 9 |
| Alternative oxide treatments and surface finishes for high-frequency operation/low skin depths | 5 | 6 | 7 | 8 |
Glass | Continued development of lower Dk glass and glass alternatives (e.g., quartz) | 4 | 5 | 6 | 8 |
Backplane architecture | Traditional backplane with increasing layer counts | 8 | 9 | 9 | 9 |
| Fly-over/cabled backplane | 6 | 7 | 8 | 9 |
| Backplane connections without re-timers | 6 | 7 | 8 | 9 |
| 3D printing | 3 | 4 | 5 | 6 |
| More layers technologies | 6 | 7 | 8 | 9 |
Energy (performance) | Liquid cooling solutions move to immersive | 7 | 8 | 9 | 9 |
| New surface finishes/solder masks | 6 | 7 | 8 | 9 |
| Heavy, thicker board architectures | 8 | 9 | 9 | 9 |
| Graphene-based solutions for thermal interface materials | 2 | 3 | 4 | 5 |
Device pin pitch | Refinement of registration systems | 6 | 7 | 8 | 9 |
| Investment in advanced plating | 5 | 6 | 7 | 8 |
| Improved materials for dimensional stability | 4 | 5 | 6 | 7 |
| Assembly solutions for better registration, using artificial intelligence (AI) and machine learning (ML) | 5 | 6 | 7 | 8 |
Performance characteristics of dielectric materials used in stackups will evolve to manage higher speeds and data rates. The manifestation of those refinements will also impact design and process improvements in thicker multilayer boards. This includes, but is not restricted to, higher layer counts, thinner dielectrics, tighter line width control, better registration, implementation of smoother copper and alternative oxide process.
As for evolution of processes, more use of additive and semi-additive technologies will emerge in parallel with this activity.
As the need for speed continues to increase, specific novel concept alternatives will come into focus,
namely use of fly-over cables or optical solutions. Research on higher conductivity solutions like graphene, will also continue.
Synergies between computer-aided design (CAD) layout tools and computer-aided manufacturing (CAM) front end design are needed to resolve simulated and real-life models envisaged by designers and realized by fabricators. The concept of digital twins is one of the possible better design practices ahead.