Central Process Unit (CPU) Socket Interconnect

CPU Socket Interconnect Key Technology Trends

Future CPU socket technology needs, especially for data center applications, should be driven based on key industry technology trends.

1. Pin count scaling: As seen in Figure 1, pin count trend over time is in an exponential trend. This exponential growth is being driven by an increase in total compute power, memory and input output (I/O) signaling bandwidth over the years.

2. Land grid array (LGA) socket mechanical loading: With the exponential increase in pin count, there is an exponential increase in total mechanical load required to maintain higher signal fidelity and low resistance contact with the package as shown in Figure 2. This increase in load drives enabling hardware complexity, costs and more importantly, socket mother board keep out area, which could impact overall compute density per motherboard.

3. Pin pitch scaling: While the server pin count scaling is exponential, server socket pitch scaling is limited, as shown in Figure 3. Reduction in pin pitch is limited due to mother board type-3 printed circuit board (PCB) manufacturing challenges[1]. This limitation is driving bigger sockets and CPU packages, which could impact socket warpage, pick and placement and handling of the socket on the motherboard and during surface mount assembly.

4. Increase in memory and high speed I/O data rates: There is an exponential increase in data rates, e.g., peripheral component interconnect express (PCIe) as shown in Figure 4. The data rate increase is forcing lower height sockets to meet high speed signaling integrity requirements. The reduction in socket height brings additional complexity to LGA pin designs to meet mechanical requirements as well as forcing higher warpage in sockets which is a potential interconnect issue at LGA to board interfaces.

Other considerations, e.g., per pin current carrying capability requirements also need to be considered to meet CPU die/package power delivery requirements.  

Technical Needs, Gaps and Solutions

The technology issues surrounding CPU sockets, the associated needs, technology status of those needs, as well as gaps and challenges to overcome, are summarized below. The time period considered is from 2024 to 2034.

Technology Status Legend

For each need, the status of today’s technology is indicated by label and color as follows:

Table 1. CPU Socket Interconnect Gaps, and Today’s Technology Status with Respect to Current and Future Needs

Commentary: Data rates are doubling every generation. Need height scaling for low loss, low impedance socket interconnects (*CMT=compression mount, *SMT=surface mount, LGA=Land grid array).

Commentary: Server pin count scaling is exponential but pitch scaling is limited by type 3 PCB design rules, which drives bigger sockets, posing a challenge for overall server platform fit. Need to drive innovation in boards and sockets to scale pitch along with pick-and-place equipment and handling capability.

Commentary: Pin-count scaling is driving higher loads. Need to drive lower per contact force to be able to reduce loads.

Commentary: Server sockets are getting bigger and thinner. Need to control warpage to ensure package-socket mating.

Commentary: Server sockets are getting bigger and thinner, with pin pitch shrinking. Need to control ball grid array (BGA) ball coplanarity for acceptable surface mount assembly.

Commentary: With compute power going up, need higher current carrying capability per pin.

DPPM = Defective parts per million

Figure 5.                  Examples of warpage measurement from Shadow Moiré and Finite Element Analysis (FEA) modeling[2]

Approaches to address Needs, Gaps and Challenges

Table 2 considers approaches to address the above needs and challenges. The evolution of these is projected out over a 10-year timeframe using technology readiness levels (TRLs).

Table 2. CPU Socket Potential Solutions

Summary

• For current low pin count(LCP) materials, the CTE is not uniform, with the CTE about five times different between flow direction and transverse direction. This makes the socket flatness issues worse. Due to these non-isotropic characteristics, the injection molding tool design such as gate numbers, locations, molding conditions and housing part feature design can possibly be optimized to mitigate the flatness problem.

• During the early socket development stage, FEA computer simulation and Shadow Moiré physical measurement can be helpful for better control of the flatness.

• Dividing a large socket into 2 pieces or multiple pieces could also mitigate the warpage concern.

• As socket height reduces over time, the material strength of the contact base metal needs to improve. This material strength improvement consideration is also correlated with socket flatness.

• Under limitations of geometry and part design, certain optimizations can be done such as in material selection, socket manufacturability and pin arm length design versus signal integrity (SI) considerations. However, the requirement for the contact to be more compliant is not good for SI performance in general.

• With higher power design requirements down the road, current density per pin will be increased to satisfy SI and power integrity needs. Different geometries and materials for SI and Power integrity are under research and development to satisfy these requirements.

References

1. Intel Xeon Processor Scalable Family, Thermal Mechanical specification and Design Guide, Dec 2019.

2. Ooi Renn Chan & Wendy Xu, “High Density Interconnect Socket Warpage Prediction and Characterization End-of-Project Webinar”, iNEMI Warpage Characterization and Management Program, April 2022, https://thor.inemi.org/webdownload/2022/Projects/HDI_Socket_Warp_EOP.pdf.

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