Laminates
Introduction
The term “laminates,” in its simplest and most general terms, refers to the combination of organic and inorganic, conductive and non-conductive materials that form the substrate upon which conducive patterns are formed and separated by dielectrics. These materials are processed and combined in circuit manufacturing processes to create
(a) printed circuit boards and
(b) integrated circuit (IC) substrates upon which semiconductors are packaged.
The dielectric material is typically composed of a combination of polymers, cross-linking and curing agents, and additives such as inorganic fillers. They may be reinforced, typically with woven fiberglass cloth, or unreinforced to form a copper clad film-based laminate.
Copper-clad laminates (CCL) refer to a dielectric material bonded to sheets of copper foil.
Prepregs refer to combinations of the polymer resin system and reinforcement used to bond layers of circuitry together. Alternatively, unreinforced resin systems are increasingly being used in IC substrate manufacturing and are referred to as bond-films or build-up films when the multilayer circuits are formed in a sequential build-up process.
While the combination of copper, resin system and reinforcement may seem quite simple, the number of variants in each of these components leads to a nearly infinite number of combinations. Each of these components can have a significant impact on critical properties, including
(a) electrical properties like the dielectric constant (Dk) and dissipation or loss factor (Df),
(b) thermomechanical properties such as the glass transition temperature (Tg), coefficients of thermal expansion (CTEs) and dimensional stability during processing, thermal conductivity, and
(c) reliability properties such as the resistance to conductive anodic filament (CAF) formation.
Substrate and raw material suppliers must continue to develop new technologies that enable future applications, including
smooth copper foils that reduce conductor losses at high frequencies,
chemical adhesion promotors to bond dielectrics to these smooth foils or to bond to fully additive metallizations, lower Dk polymers, and
new fillers and reinforcements that improve electrical properties, reduce thermal expansion properties and maintain flatness throughout the manufacturing processes.
It is growing increasingly challenging to simultaneously optimize for all of these properties in order to meet the requirements of ever-more complex electronics designs, support high-volume manufacturing processes and meet sustainability goals.
Technical Needs, Gaps and Solutions
The technology issues surrounding laminates, the associated needs, technology status of those needs, as well as gaps and challenges to overcome, are summarized below. The time period considered is from 2025 to 2035.
Technology Status Legend
For each need, the status of today’s technology is indicated by label and color as follows:
In-table color + label key | Description of Technology Status |
|---|---|
Solutions not known | Solutions not known at this time |
Solutions need optimization | Current solutions need optimization |
Solutions deployed or known | Solutions deployed or known today |
Not determined | TBD |
Table 1. Laminate-based Semiconductor Packaging (Substrates) Needs, Gaps, and Today’s Technology Status with Respect to Current and Future Needs
| ROADMAP TIMEFRAME | |||
TECHNOLOGY ISSUE | TODAY (2025) | 3 YEARS (2028) | 5 YEARS (2030) | 10 YEARS (2035) |
ISSUE #1 Build-up Miniaturization (pitch, line width, etc., hole size, thickness, aspect ratio) as “Node” Generations | ||||
Optical resolution node/feature sizes | ||||
NEED: Reduced pitch sizes (Most advanced packaging given here) 1 | 200 um (core) | 190 um (core) | 170 um (core) | 150 um (core) |
NEED Adoption of modified or semi-additive processing (carrier foil, seeding, etc.) | Modified semi-additive process (MSAP) and semi-additive process (SAP) – carrier foils | Direct metallization MSAP | Improved MSAP with desired resolution, impedance control with higher density, more layers | Refined, at scale- MSAP with less variation for desired resolution, impedance control, higher density, more layers, and flatness approaching the packaging/board capabilities |
CURRENT TECHNOLOGY STATUS | Solutions deployed | Solutions need optimization | Solutions not known | |
GAP | Low adhesion and lack of uniform morphology (e.g., plating at smaller, finer pitches, transition materials leading to signal integrity issues) | |||
CHALLENGES | Core material mfg. with good alignment at many levels. Flatness variability. CTE and contact alignment. | Cost of tooling. Agreement for equipment standards | ||
Adhesion (structural integrity and device mounting, copper) | New materials for heat mitigation. New, higher-resolution optics (laser directed imaging and non- contact) for processing | |||
NEED Registration/alignment of circuit features (buildup with core) | Standard materials exist through JEDEC, e.g., Ajiamoto build-up film (ABF), epoxy at high-volume manufacturing (HVM) | Alternatives to ABF with better properties / better resolution capability | New, better materials are dominant/adopted | Progression of standard new materials as mix-media applications (e.g., high frequency applications) |
NEED CTE (core)1 | 6 ppm/K (xy) | 4 ppm/K (xy) 15 ppm/K (z) | 3 ppm/K (xy) 15 ppm/K (z) | 3 ppm/K (xy) 15 ppm/K (z) |
NEED CTE (build-up)1 | 20 ppm/K (xy & z) | 15 ppm/K (xy & z) | 10 ppm/K (xy & z) | 10 ppm/K (xy & z) |
CURRENT TECHNOLOGY STATUS | Deployed | In development, low-volume manufacturing (LVM) deployed | To be optimized |
|
GAP | Low variety of material solutions for low-loss, lower dielectric constant | Tooling and process development lead-time | HVM at high yield | |
CHALLENGES |
| Repeatability, reliability of alternatives | ||
Limited suppliers for alternatives, intellectual property (IP) challenges (patent “moat”) | ||||
NEED Mechanical and electrical operational performance stability (reliability, bonds, signal integrity, etc.) over a temperature range | Sustained high performance in harsh operating environments (extremes) MOT (maximum operating temperature): 150°C Minimum operating temp: -55°C | More of a multi-dimensional approach in place, such as: Thermal management, weak link properties addressed, and improved choice of materials for the full temperature ranges with alternative designs and methods for harsh environment protection MOT: 160°C | ||
CURRENT TECHNOLOGY STATUS | Using what is in hand today but with tradeoffs like performance needs, material properties, etc. | Solutions to be aligned and integrated, with thermal management and protections for circuitry heat dissipation as well as environment | ||
GAP | Extended harsh environments below | New approaches affect business operations and return on investment (ROI) so little demand for change | ||
CHALLENGES | Materials properties (e.g., oxidative properties of polymers, “slippery” materials mixes, organic to metal bonds, etc.) with “weak links”, such as mechanical adhesion, metal reliability, and processes for these | Single-material solutions have good performance for a limited set of properties. | ||
No standards and equivalency specs for MOT testing, and functional high-temperature testing (e.g., accelerated aging tests for harsh environments) | ||||
ISSUE # 2 Yield at HVM | ||||
NEED | Testing procedures evolution (methods and specs for new products) | Extending existing and developing new testing procedures (methods and specs for new products) | Developing new testing procedures (methods and specs for new products) | |
CURRENT TECHNOLOGY STATUS | Extending existing standards and procedures | |||
GAP | Establishing acceptance criteria | TBD | ||
CHALLENGES | Decisions for methods extended or developed for new processes, materials | Complexity of architectures and materials | ||
Lead time for validation processes | ||||
Trade-offs for electrical performance improvement | ||||
ISSUE #3 Processes | ||||
NEED | Interconnect size getting smaller for handheld devices: maintain hole quality in preparation and drilling | Interconnect size getting smaller for handheld and large format devices: maintain hole quality in preparation and drilling | Introduce homogenous materials (e.g., resin-coated Cu foil) to enable further reductions in interconnect size | |
CURRENT TECHNOLOGY STATUS | Solutions known | Solutions need optimization | Solutions not known | |
GAP | Some handheld manufacturers already at minimum sub-3 mil drilled and 1.5 mil. | Low maturity of printing and nanotech approaches | ||
CHALLENGES | Investment cost | Investment and manufacturing at scale | ||
At the limit of mechanical drilling (e.g., limits of spindle speed). | New drilling approaches needed below 200,um. | |||
Equipment needs to improve the cleaning/gas bumping methods. | ||||
NEED | Thermal cycling tests (esp. with mechanical drilling 0.15 mm) to meet requirements as geometries get smaller /aspect ratios get higher. | Higher hole density, smaller holes – now primarily with laser drilling, with new dielectric materials, including thickness control. | ||
CURRENT TECHNOLOGY STATUS | JEDEC standards in field, solutions being optimized | Development for new materials underway | ||
GAP | Design features and reliability requirements still not clear | MSAP to fully additive bonding with new materials and processes | ||
CHALLENGE | Copper to dielectric adhesion becomes more challenging, and lower loss, due to smooth surfaces result in bonding issues | |||
NEED | Improved clean room environment and handling solutions for smaller features, MSAP, etc. | Improved recertification for infrastructure for manufacturing (e.g., cleanroom, more accurate machines and handling, reduced machine-induced ESD, etc.) | ||
TECHNOLOGY STATUS | Solutions to be upgraded and evolve | |||
GAP | ||||
CHALLENGE | Heavy investment required for facilities | |||
ISSUE #4 Larger package sizes for heterogeneous integration. | ||||
NEED | Controlled warpage with larger package size | Allowable microns per millimeter to be reduced (Refer to Board Assembly Roadmap, CPU Socket, Issue #4) | ||
CURRENT TECHNOLOGY STATUS | Optimization is continual | |||
GAP | Conflicting needs and tradeoffs between electrical versus thermal/mechanical | |||
CHALLENGES |
| Larger size packages continue and total warpage increases because of CTE mismatch and copper uniformity challenges due to power delivery challenges, and asymmetric stacking increases. | ||
ISSUE #5 Thermal stability for high-reliability connections in heterogeneous integration. | ||||
NEED | x, y, and now z-axis thermal expansion needs to be limited | |||
CURRENT TECHNOLOGY STATUS | To be optimized – base material leading-edge application | |||
GAP | Limit to use of inorganic fillers in organic substrates for CTE reduction | |||
CHALLENGE | Designing the resin system: how to achieve high packing density with inorganic fillers, but also without compromising structural integrity, adhesion or Dk. | Miniaturization will be a challenge | ||
ISSUE #6 Materials (Copper, etc.) | ||||
NEED | Thinner Cu foils (3 um) on a carrier foil. | Thin Cu layer (<1 um) deposited (SAP) on a dielectric coating | 0.1 um with SAP approach | Purely additive approach |
CURRENT TECHNOLOGY STATUS | ||||
GAP | Consistency of background etching and adhesion | Adhesion and plating additively into a pattern | ||
CHALLENGE | Moving from a prototype process to production | Difficult to achieve the necessary chemical bond with an organic surface. Lower loss materials have worse adhesion. | ||
ISSUE #7 Testability/Inspection (AOI) | ||||
NEED | Classifying and certifying laminate prior to shipping: Automated optical inspection (AOI) with high-resolution optics to enable automation and speed, to determine thickness and detect imperfections | Finer features driving new quality classes and more accurate/finer classification (e.g., detect <0.5 mil and lower imperfections) | ||
CURRENT TECHNOLOGY STATUS | Solutions deployed | Solutions need optimization | ||
GAP | Level of automation to operate at scale | |||
CHALLENGE | None | |||
ISSUE #8 Performance (speed) | ||||
NEED | Lower Dk, Df for the substrate. Df = 0.01-0.009 | Df = 0.006 | Below Df = 0.003 | |
CURRENT TECHNOLOGY STATUS | ||||
GAP | New blends or new material needed for core. | New materials needed. | ||
CHALLENGE | Lower range of choices for the core. | |||
ISSUE #9 Assembly | ||||
NEED | High I/O Pin Counts with Smaller Pin Pitch | |||
CURRENT TECHNOLOGY STATUS | Large infrastructure at .65 mm diagonal, small boards are .3 mm | High-density interconnector (HDI), .5 for big boards, and for small boards “substrate-like” dimensions (board becomes substrate) | Built for long life (>10 years) | |
GAP | Lack of design rules for below current pitch limits and for small boards with small features (.3 mm) | Lack of stable supply and repeatability/ consistency | Test methodology for long-life | |
CHALLENGE | High-layer count forcing the emergence of fine lines and tighter signal integrity margins | Capability and reliability of copper and glass replacements and new materials at scale | ||
CHALLENGE | Power to drive signals. Higher thermal resistance (Higher Tg and lower CTE materials). | |||
ISSUE #11 Sustainability | ||||
Approaches to address Needs, Gaps and Challenges
Table 2 considers approaches to address the above needs and challenges. The evolution of these is projected out over a 10-year timeframe using technology readiness levels (TRLs).
In-table color key | Range of Technology Readiness Levels | Description |
|---|---|---|
2 | TRL: 1 to 4 | Levels involving research |
6 | TRL: 5 to 7 | Levels involving development |
9 | TRL: 8 to 9 | Levels involving deployment |
Table 2. Laminate-based Semiconductor Packaging (Substrates) Potential Solutions
|
| EXPECTED TRL LEVEL* | |||
TECHNOLOGY ISSUE | POTENTIAL SOLUTIONS |
TODAY (2025) | 3 (2028) | 5 (2030) | 10 |
Build-up processes for miniaturization (pitch, line width, etc., hole size, thickness, aspect ratio) | Stay current with state of art equipment | 7 | 8 | 9 | 9 |
Invest in semi-additive solutions and processes (i.e., Cu deposition on dielectric coating with Pd) | 6 | 7 | 8 | 8 | |
Continue development and deployment of high aspect ratio (AR) drilling and laser ablation, plating and cleaning methods (plasma desmear) | 7 | 8 | 9 | 9 | |
Higher spindle speeds, new entry materials for better performance for mechanical drilling and machinery enhancements (e.g., spindle cooling, alternative environments (vacuum), etc.) | 7 | 8 | 8 | 9 | |
High yield at HVM (Narrower process window) | Increased automation (e.g., auto-layup, etc.) | 5 | 6 | 7 | 8 |
Clean room enhancements and investment | 5 | 6 | 7 | 8 | |
Smart manufacturing floor (e.g., artificial intelligence (AI) feedback loop to improve process control and yield) | 6 | 7 | 8 | 8 | |
Current materials less capable | Increased capability in materials (e.g., quartz glass, CTE [x, y, z], Tg, Df and Dk, dielectric strength, bond-ability, etc.) | 6 | 7 | 8 | 9 |
Improve thermal stability for current materials (e.g., like glass interposers, etc.) | 6 | 7 | 8 | 9 | |
Flatness stability improves with materials and process enhancements | 6 | 7 | 8 | 9 | |
Conclusions
Development of alternative higher reliability and specialized laminates and materials to help support and sustain printed circuit board (PCB) and substrate development in the future need to occur to drive necessary performance (e.g., speed, dimensional control, flatness, overall quality, sustained reliability at HVM, and thermal management attributes). Key technologies to address are as follows:
Continued evolution of semi-additive technologies (SAP/MSAP) are critical for addressing miniaturization, impedance control, flatness, adhesion qualities, and performance/reliability (e.g., crosstalk, etc.).
Continued evolution of thinner, lower Dk and Df, and tougher dielectrics and laminate supplies (e.g., glass, non-glass, etc.)
Continued evolution of higher resolution photoimaging and higher reliability materials
Improved drilling capability of new materials and drilling process parameters needs to be investigated and developed (e.g., cleaning, achieving high AR, machineability, stacked via ability/reliability, build-up layer technologies, etc.)
Address critical challenge(s) in finding the right mix of materials, drilling technologies, and hole wall cleaning technologies to achieve ever more stringent requirements of miniaturization (e.g., for registration, thinness, etc.)
Process innovation for smaller features will also drive investments for improved clean-room environments, increased machine and handling accuracy, and reductions in equipment-induced ESD. More stringent auditing and certification will also follow.
Laminates will require/exploit automation and smart manufacturing to improve yield for high volume manufacturing; significant investment is required.
Model-based solutions will be needed.
Will have an impact on the supply chain landscape (small versus large and/or narrow versus broader-based suppliers) that opens the door for innovation and possible cross-over solutions from other industries
Laminate materials over the next 5-10 years requires electrical, mechanical and thermal improvements (Challenges are the trade-offs with these). Leakage, CAF, electro-migration are key issues.
Materials’ selection includes sustainability considerations
Thermal conductivity and heat capacity and removal for laminate materials and films and processes will remain a challenge as circuit densification/miniaturization continue to evolve.
Speed of technology innovation in laminates will be driven by the application domains with the fastest evolution. Today, these are mobile handsets and AI processor boards. More conservative application markets, e.g. aeronautics, will be slower to roll out less developed materials and processes.
PCB Acronyms
References
JPCA, JPCA PWB Technology Roadmap, 2023.